Abstract
Microstructure analysis plays an important role in the reliability study of copper Through-Silicon Vias (TSVs). While conventional 2-dimensional (2D) Electron Back-Scatter Diffraction (EBSD) is a useful technique, 3-dimensional (3D) EBSD characterization provides a more accurate picture of the TSV microstructure. Information that is missing in 2D observations, such as grain shape and volume, can be obtained from the 3D technique. In this study, we did 3D characterizations by serial sectioning of the TSV samples and mapped the microstructure on each slice. These maps were then reconstructed into 3D images. From the result, it showed that the increase in Cu grain volume after thermal annealing can be up to 99%, as compared with 55% and 67% increase in calculated grain volume as determined from single and averaged 2D EBSD maps, respectively.
Original language | English |
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Title of host publication | Proceedings of the 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2014 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 295-299 |
Number of pages | 5 |
ISBN (Electronic) | 9781479939091 |
DOIs | |
Publication status | Published - Sept 12 2014 |
Externally published | Yes |
Event | 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2014 - Singapore, Singapore Duration: Jun 30 2014 → Jul 4 2014 |
Publication series
Name | Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA |
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Conference
Conference | 21th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2014 |
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Country/Territory | Singapore |
City | Singapore |
Period | 6/30/14 → 7/4/14 |
Bibliographical note
Publisher Copyright:© 2014 IEEE.
ASJC Scopus Subject Areas
- Electrical and Electronic Engineering