A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in Series-Connected Two-Dimensional Transistors

Multiple-valued logic (MVL) is highly desired for algebra, logic, and artificial intelligence due to its higher information density. However, its practical adoption has been hindered for decades by extensive hardware requirements. Two-dimensional (2D) materials with exceptional electronic properties provide possibilities for the development of MVL devices with simple structures. Despite several reports on ternary logic (r = 3) hardware, extending their design to higher logic radix devices (r > 3) is challenging. The construction of elementary MVL gates with a higher radix is still relatively underexplored, and a universal device implementation approach is lacking. In this study, we exploit transconductance (g_m) matching between the negative transconductance (NTC) effect in series-connected molybdenum disulfide (MoS₂) and black phosphorus (BP) transistors, along with the multiple current valleys of BP transistors, to realize a series of multivalued logic (MVL) gate families (r = 3, 4, 5). Our design achieves reduced transistor counts, higher DC gains, and lower power consumption. Standard quaternary (r = 4) and quinary (r = 5) inverters are demonstrated using only four and five planar transistors, respectively. Additionally, compact models of 2D transistors and equivalent circuits of the MVL gate are established, supporting future large-scale MVL system design and simulation.