@inproceedings{22713e5a48294cd6a8555018cc1623c6,
title = "Advanced STI technology with void free gap-fill and superior device performance for 45nm devices",
abstract = "The gap-fill capability of HARP process is not only controlled by the O3/TEOS ratio of HARP deposition, but also strongly influenced by the STI trench profile and annealing conditions. HARP prefers a V-shaped STI trench profile with ≤ 86° slope for better gap-fill. Steam annealing will help to repair seam or tiny pinhole formed inside the trench after HARP deposition but the steam annealing temperature and time need to be strictly controlled to alleviate active Si loss. Replacing HDP with HARP for STI leads to a significant improvement of drive current for both nFET and pFET narrow width transistor because of tensile strain induced by HARP. Annealing condition shows dramatic impact on the tensile strain intensity inducing to Si. The tensile Si strain induced by HARP has been verified by micro-Raman spectroscopy.",
author = "H. Liu and L. Wong and W. Lu and Sun, {Z. G.} and I. Bangun and Shen, {Y. P.} and Wu, {Y. P.} and Z. Chen and Zhou, {M. S.} and T. Chu and R. Leong and A. Jain and C. Ching and K. Raguputhi and H. Whitesell and J. Kasim and Z. Shen",
year = "2006",
language = "English",
isbn = "9889884445",
series = "Semiconductor Technology, ISTC2007 - Proceedings of the 6th International Conference on Semiconductor Technology",
publisher = "Electrochemical Society",
pages = "81--87",
booktitle = "Semiconductor Technology, ISTC2007 - Proceedings of the 6th International Conference on Semiconductor Technology",
note = "6th International Conference on Semiconductor Technology, ISTC2007 ; Conference date: 18-03-2007 Through 20-03-2007",
}