Area-constrained technology mapping for in-memory computing using ReRAM devices

Debjyoti Bhattacharjee; Arvind Easwaran; Anupam Chattopadhyay

doi:10.1109/ASPDAC.2017.7858298

Area-constrained technology mapping for in-memory computing using ReRAM devices

Debjyoti Bhattacharjee, Arvind Easwaran, Anupam Chattopadhyay

Nanyang Technological University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

11 Citations (Scopus)

Abstract

In-memory computing platforms, such as Resistive RAM (ReRAM), offer natural advantage to data-intensive applications. The benefits of data locality and capability to perform native Boolean operations is exploited for significant performance advantage in multiple contexts ranging across neuromorphic computing, associative memory-based computing, arithmetic benchmarks and general-purpose programmable logic-in-memory computing. Despite these advances, design automation tools supporting in-memory computing are still in a nascent phase. In this work, we investigate for the first time, the problem of minimizing delay under arbitrary area constraint of ReRAM devices. We formulate the problem of area-constrained delay minimization as an Integer Linear Programming (ILP) formulation and further propose heuristics that offers scalability as well as solution close to optimal performance. Areaconstrained mapping technology mappings enables unlocking significantly large design space trade-offs.

Original language	English
Title of host publication	2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	69-74
Number of pages	6
ISBN (Electronic)	9781509015580
DOIs	https://doi.org/10.1109/ASPDAC.2017.7858298
Publication status	Published - Feb 16 2017
Externally published	Yes
Event	22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 - Chiba, Japan Duration: Jan 16 2017 → Jan 19 2017

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017
Country/Territory	Japan
City	Chiba
Period	1/16/17 → 1/19/17

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

ASJC Scopus Subject Areas

Electrical and Electronic Engineering
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ASPDAC.2017.7858298

Cite this

Bhattacharjee, D., Easwaran, A., & Chattopadhyay, A. (2017). Area-constrained technology mapping for in-memory computing using ReRAM devices. In 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017 (pp. 69-74). Article 7858298 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2017.7858298

Bhattacharjee, Debjyoti ; Easwaran, Arvind ; Chattopadhyay, Anupam. / Area-constrained technology mapping for in-memory computing using ReRAM devices. 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 69-74 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

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Bhattacharjee, D, Easwaran, A & Chattopadhyay, A 2017, Area-constrained technology mapping for in-memory computing using ReRAM devices. in 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017., 7858298, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, Institute of Electrical and Electronics Engineers Inc., pp. 69-74, 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, 1/16/17. https://doi.org/10.1109/ASPDAC.2017.7858298

Area-constrained technology mapping for in-memory computing using ReRAM devices. / Bhattacharjee, Debjyoti; Easwaran, Arvind; Chattopadhyay, Anupam.
2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 69-74 7858298 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Bhattacharjee D, Easwaran A, Chattopadhyay A. Area-constrained technology mapping for in-memory computing using ReRAM devices. In 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 69-74. 7858298. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2017.7858298

Area-constrained technology mapping for in-memory computing using ReRAM devices

Abstract

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Bibliographical note

ASJC Scopus Subject Areas

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