Design & Implementation of All Digital I-Q Modulator and Demodulator for High Speed WLAN in FPGA

Basuki Endah Priyanto; Choi Look Law; Yong Liang Guan

Design & Implementation of All Digital I-Q Modulator and Demodulator for High Speed WLAN in FPGA

Basuki Endah Priyanto^*, Choi Look Law, Yong Liang Guan

^*Corresponding author for this work

Nanyang Technological University

Research output: Contribution to conference › Paper › peer-review

4 Citations (Scopus)

Abstract

The project aims to provide the front-end digital signal processing functions in a quadrature modem for IEEE 802.11a WLAN test-bed. The design and implementation of a pair of all digital I-Q modulator and demodulator suitable for high-speed wireless communication is discussed. The effects of finite bit resolution are considered in the implementation of both modulator and demodulator. Each of them is integrated with 40-tap FIR square root raised cosine filter with excess bandwidth 0.15. There are several issues that needed to be considered in the real implementation in FPGA to achieve the goal of a real time implementation. The system clock needs to run at least 80 MHz to perform real time signal processing. Both modulator and demodulator utilize a total of 120K FPGA equivalent gates, which is only 2 % of available logic of a Xilinx FPGA XC2V-6000. The all-digital modem in FPGA results in a very flexible chipset.

Original language	English
Pages	659-662
Number of pages	4
Publication status	Published - 2003
Externally published	Yes
Event	2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003) - Victoria, B.C., Canada Duration: Aug 28 2003 → Aug 30 2003

Conference

Conference	2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003)
Country/Territory	Canada
City	Victoria, B.C.
Period	8/28/03 → 8/30/03

ASJC Scopus Subject Areas

Signal Processing
Computer Networks and Communications

Cite this

@conference{4533bc90dc194dee855ba163844ebb67,

title = "Design & Implementation of All Digital I-Q Modulator and Demodulator for High Speed WLAN in FPGA",

abstract = "The project aims to provide the front-end digital signal processing functions in a quadrature modem for IEEE 802.11a WLAN test-bed. The design and implementation of a pair of all digital I-Q modulator and demodulator suitable for high-speed wireless communication is discussed. The effects of finite bit resolution are considered in the implementation of both modulator and demodulator. Each of them is integrated with 40-tap FIR square root raised cosine filter with excess bandwidth 0.15. There are several issues that needed to be considered in the real implementation in FPGA to achieve the goal of a real time implementation. The system clock needs to run at least 80 MHz to perform real time signal processing. Both modulator and demodulator utilize a total of 120K FPGA equivalent gates, which is only 2 % of available logic of a Xilinx FPGA XC2V-6000. The all-digital modem in FPGA results in a very flexible chipset.",

author = "Priyanto, {Basuki Endah} and Law, {Choi Look} and Guan, {Yong Liang}",

year = "2003",

language = "English",

pages = "659--662",

note = "2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003) ; Conference date: 28-08-2003 Through 30-08-2003",

}

Design & Implementation of All Digital I-Q Modulator and Demodulator for High Speed WLAN in FPGA. / Priyanto, Basuki Endah; Law, Choi Look; Guan, Yong Liang.
2003. 659-662 Paper presented at 2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003), Victoria, B.C., Canada.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Design & Implementation of All Digital I-Q Modulator and Demodulator for High Speed WLAN in FPGA

AU - Priyanto, Basuki Endah

AU - Law, Choi Look

AU - Guan, Yong Liang

PY - 2003

Y1 - 2003

N2 - The project aims to provide the front-end digital signal processing functions in a quadrature modem for IEEE 802.11a WLAN test-bed. The design and implementation of a pair of all digital I-Q modulator and demodulator suitable for high-speed wireless communication is discussed. The effects of finite bit resolution are considered in the implementation of both modulator and demodulator. Each of them is integrated with 40-tap FIR square root raised cosine filter with excess bandwidth 0.15. There are several issues that needed to be considered in the real implementation in FPGA to achieve the goal of a real time implementation. The system clock needs to run at least 80 MHz to perform real time signal processing. Both modulator and demodulator utilize a total of 120K FPGA equivalent gates, which is only 2 % of available logic of a Xilinx FPGA XC2V-6000. The all-digital modem in FPGA results in a very flexible chipset.

AB - The project aims to provide the front-end digital signal processing functions in a quadrature modem for IEEE 802.11a WLAN test-bed. The design and implementation of a pair of all digital I-Q modulator and demodulator suitable for high-speed wireless communication is discussed. The effects of finite bit resolution are considered in the implementation of both modulator and demodulator. Each of them is integrated with 40-tap FIR square root raised cosine filter with excess bandwidth 0.15. There are several issues that needed to be considered in the real implementation in FPGA to achieve the goal of a real time implementation. The system clock needs to run at least 80 MHz to perform real time signal processing. Both modulator and demodulator utilize a total of 120K FPGA equivalent gates, which is only 2 % of available logic of a Xilinx FPGA XC2V-6000. The all-digital modem in FPGA results in a very flexible chipset.

UR - http://www.scopus.com/inward/record.url?scp=0142168884&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0142168884&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0142168884

SP - 659

EP - 662

T2 - 2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003)

Y2 - 28 August 2003 through 30 August 2003

ER -

Design & Implementation of All Digital I-Q Modulator and Demodulator for High Speed WLAN in FPGA

Abstract

Conference

ASJC Scopus Subject Areas

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