Dynamic write-level and read-level signal design for MLC NAND flash memory

Chaudhry Adnan Aslam; Yong Liang Guan; Kui Cai

doi:10.1109/CSNDSP.2014.6923850

Dynamic write-level and read-level signal design for MLC NAND flash memory

Chaudhry Adnan Aslam^*, Yong Liang Guan, Kui Cai

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

In this paper, we propose dynamic write-level and read-level voltage scheme for MLC NAND flash memory. We study the characteristics of flash channel which can be modeled as mixture of Uniform and Exponential distribution. Since this channel shows non-stationary behavior, we present probability of error analysis and introduce the concept of dynamically adjusting the verify-level (write-level) and quantization-level (read-level) voltage values over varying flash channel. The proposed dynamic voltage based method outperforms fixed verify-level voltage scheme. We demonstrate improvements in bit-error-rate (BER) performance and cell storage capacity for the proposed signal design scheme.

Original language	English
Title of host publication	2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	336-341
Number of pages	6
ISBN (Electronic)	9781479925810
DOIs	https://doi.org/10.1109/CSNDSP.2014.6923850
Publication status	Published - Oct 14 2014
Externally published	Yes
Event	2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014 - Manchester, United Kingdom Duration: Jul 23 2014 → Jul 25 2014

Publication series

Name	2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014

Conference

Conference	2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014
Country/Territory	United Kingdom
City	Manchester
Period	7/23/14 → 7/25/14

Bibliographical note

Publisher Copyright:
© 2014 IEEE.

ASJC Scopus Subject Areas

Signal Processing
Computer Networks and Communications

Keywords

BER
MLC NAND Flash
PE
quantization-level
verify-level

Access to Document

10.1109/CSNDSP.2014.6923850

Cite this

Aslam, C. A., Guan, Y. L., & Cai, K. (2014). Dynamic write-level and read-level signal design for MLC NAND flash memory. In 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014 (pp. 336-341). Article 6923850 (2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CSNDSP.2014.6923850

Aslam, Chaudhry Adnan ; Guan, Yong Liang ; Cai, Kui. / Dynamic write-level and read-level signal design for MLC NAND flash memory. 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 336-341 (2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014).

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abstract = "In this paper, we propose dynamic write-level and read-level voltage scheme for MLC NAND flash memory. We study the characteristics of flash channel which can be modeled as mixture of Uniform and Exponential distribution. Since this channel shows non-stationary behavior, we present probability of error analysis and introduce the concept of dynamically adjusting the verify-level (write-level) and quantization-level (read-level) voltage values over varying flash channel. The proposed dynamic voltage based method outperforms fixed verify-level voltage scheme. We demonstrate improvements in bit-error-rate (BER) performance and cell storage capacity for the proposed signal design scheme.",

keywords = "BER, MLC NAND Flash, PE, quantization-level, verify-level",

author = "Aslam, {Chaudhry Adnan} and Guan, {Yong Liang} and Kui Cai",

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Aslam, CA, Guan, YL & Cai, K 2014, Dynamic write-level and read-level signal design for MLC NAND flash memory. in 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014., 6923850, 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014, Institute of Electrical and Electronics Engineers Inc., pp. 336-341, 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014, Manchester, United Kingdom, 7/23/14. https://doi.org/10.1109/CSNDSP.2014.6923850

Dynamic write-level and read-level signal design for MLC NAND flash memory. / Aslam, Chaudhry Adnan; Guan, Yong Liang; Cai, Kui.
2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 336-341 6923850 (2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - In this paper, we propose dynamic write-level and read-level voltage scheme for MLC NAND flash memory. We study the characteristics of flash channel which can be modeled as mixture of Uniform and Exponential distribution. Since this channel shows non-stationary behavior, we present probability of error analysis and introduce the concept of dynamically adjusting the verify-level (write-level) and quantization-level (read-level) voltage values over varying flash channel. The proposed dynamic voltage based method outperforms fixed verify-level voltage scheme. We demonstrate improvements in bit-error-rate (BER) performance and cell storage capacity for the proposed signal design scheme.

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Aslam CA, Guan YL, Cai K. Dynamic write-level and read-level signal design for MLC NAND flash memory. In 2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 336-341. 6923850. (2014 9th International Symposium on Communication Systems, Networks and Digital Signal Processing, CSNDSP 2014). doi: 10.1109/CSNDSP.2014.6923850

Dynamic write-level and read-level signal design for MLC NAND flash memory

Abstract

Publication series

Conference

Bibliographical note

ASJC Scopus Subject Areas

Keywords

Access to Document

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