TY - GEN
T1 - Electromigration reliability comparison of Cu and Al interconnects
AU - Alam, Syed M.
AU - Wei, Frank L.
AU - Gan, Chee Lip
AU - Thompson, Carl V.
AU - Troxel, Donald E.
PY - 2005
Y1 - 2005
N2 - Under similar test conditions, the electromigration reliability of Al and Cu metallization interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. In Cu technology, the low critical stress for void nucleation at the interface of the Cu and the inter-level diffusion barrier, such as Si/sub 3/N/sub 4/, leads to asymmetric failure characteristics based on via position in a line. Unlike Al technology, a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Using the best estimates of material parameters and an analytical model, we have compared electromigration lifetimes of Al and Cu dual-damascene interconnect lines. A reliability CAD tool, SysRel, has been used to simulate full-chip reliability of the same circuit layout with different interconnect technologies. In typical circuit operating conditions, Al bamboo lines have the best lifetime followed by Cu via-below, Cu via-above, and Al polygranular type lines.
AB - Under similar test conditions, the electromigration reliability of Al and Cu metallization interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. In Cu technology, the low critical stress for void nucleation at the interface of the Cu and the inter-level diffusion barrier, such as Si/sub 3/N/sub 4/, leads to asymmetric failure characteristics based on via position in a line. Unlike Al technology, a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Using the best estimates of material parameters and an analytical model, we have compared electromigration lifetimes of Al and Cu dual-damascene interconnect lines. A reliability CAD tool, SysRel, has been used to simulate full-chip reliability of the same circuit layout with different interconnect technologies. In typical circuit operating conditions, Al bamboo lines have the best lifetime followed by Cu via-below, Cu via-above, and Al polygranular type lines.
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U2 - 10.1109/ISQED.2005.51
DO - 10.1109/ISQED.2005.51
M3 - Conference contribution
AN - SCOPUS:84860559730
SN - 0769523013
SN - 9780769523019
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 303
EP - 308
BT - Proceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005
T2 - 6th International Symposium on Quality Electronic Design, ISQED 2005
Y2 - 21 March 2005 through 23 March 2005
ER -