Experimental and numerical studies of stress migration in Cu interconnects embedded in different dielectrics

In this work, package level stress migration (SM) test of Cu dual-damascene interconnects in via-line structures were performed. Two factors that were considered are stressing temperature and dielectric materials. The via-line structures were studied at temperatures ranging from 150°C to 250°C, with highest failure rate being detected at 200°C. In comparing stress migration data on carbon doped oxide (CDO) with undoped silica glass (USG), a difference of two orders of magnitude was detected in the rate of change of resistance. More than 40% of the CDO samples showed open circuit failures after a 1344-hour test, whereas the maximum resistance change in the USG samples was only 10%. Failure analysis based on FIB indicated that failures in both CDO & USG were very similar in nature with voids forming symmetrically at the bottom of the via, showing that the integrity of the Ta barrier in the via bottom area was of significant influence to SM. The line width of the two-level interconnects is almost the same as the via size. The observed SM phenomenon is different from the voiding under and/or inside vias connected to wide Cu line, previously referred as SIV (stress-induced voiding). Finite element analysis (FEA) indicated that the driving force for void growth, the gradient of hydrostatic stress, at via bottom in CDO structure is 30% higher than the one in USG.