Impact of non-blocking vias on electromigration and circuit-level reliability assessments of Cu interconnects

In Cu metallization, refractory metal liners at vias generally block electromigration. As liner thicknesses are decreased, fully-blocking liners at vias become less certain due to liner ruptures. We have developed and exercised a reliability CAD tool, SysRel, for circuit-level interconnect reliability assessments, and used it to assess the impact of non-blocking vias on circuit-level reliability with Cu metallization. SysRel utilizes a hierarchical reliability analysis with fundamental reliability units that sufficiently captures the differences in electromigration failure between Al and Cu metallization. This paper is the first discussion of its application to real circuit elements, to investigate the impact of non-blocking vias on circuit-level reliability. As observed in a 32-bit comparator circuit layout, the presence of non-blocking vias leads to an overall reduction in the number of mortal trees and to an increase in the effective length of the mortal trees. Full-chip reliability degrades if electromigration lifetime is treated as a strong function of line length.