Abstract
Ternary logic with larger data density has great potential in high-performance data processing. Even though ternary half/full adders have been intensively investigated in recent years, the high-speed multi-trit ternary adders, which are urgently needed for high-efficient ternary computing, remain unexplored. In this study, we present ternary carry lookahead adders (CLAs) to eliminate the tedious delay caused by the cascade-connected carry signals. Different implementation methods are used for unbalanced and balanced ternary logic. A delay analysis model of ternary CLAs is established. Compared with reported ternary carry ripple adders (CRAs), our 5-trit unbalanced and balanced ternary CLAs can achieve a 61.45% and 75.18% reduction in delay, respectively.
| Original language | English |
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| Title of host publication | 2024 IEEE 13th International Conference on Communications, Circuits, and Systems, ICCCAS 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 169-174 |
| Number of pages | 6 |
| ISBN (Electronic) | 9798350386271 |
| DOIs | |
| Publication status | Published - 2024 |
| Externally published | Yes |
| Event | 13th IEEE International Conference on Communications, Circuits, and Systems, ICCCAS 2024 - Xiamen, China Duration: May 10 2024 → May 12 2024 |
Publication series
| Name | 2024 IEEE 13th International Conference on Communications, Circuits, and Systems, ICCCAS 2024 |
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Conference
| Conference | 13th IEEE International Conference on Communications, Circuits, and Systems, ICCCAS 2024 |
|---|---|
| Country/Territory | China |
| City | Xiamen |
| Period | 5/10/24 → 5/12/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
ASJC Scopus Subject Areas
- Computer Networks and Communications
- Hardware and Architecture
- Electrical and Electronic Engineering
- Instrumentation
Keywords
- carry look ahead adder
- multiple-valued logic
- ternary logic circuits
- unbalanced and balanced ternary logic