Integration of nitrogen ion-implantation in sub-micron CMOS device fabrication process

In this paper, the effect of incorporating N⁺ ion-implantation into deep sub-micron CMOS device process is discussed. Silicide formation, contact resistance, leakage current, threshold voltage and saturation current are studied for a variety of additional N⁺ implantation steps. This is the first paper reported that silicidation reaction can be enhanced by N⁺ implantation and resulted in thicker (>30% increment) silicide formation. As a result, lower sheet resistance can be achieved on narrow poly-Si (polycrystalline silicon gate) line. Low energy and dosage ion-implantation condition is preferred in order to minimize the gate to source/drain leakage and junction leakage which will be further discussed in this paper. Impact of incorporating N⁺ implantation into conventional self-aligned TiSi₂ sub-micron CMOS devices fabrication process is presented and compared with conventional salicide (self-aligned silicide) process without N⁺ implantation.