Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates

Zhiwei Zeng; Guangchao Zhao; Xingli Wang; Beng Kang Tay; Mingqiang Huang

doi:10.1109/WSCE59557.2023.10366016

Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates

Zhiwei Zeng, Guangchao Zhao, Xingli Wang, Beng Kang Tay^*, Mingqiang Huang^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Ternary logic system has attracted more and more attention because of its higher information density as compared with the binary system. In the prevalent multi-threshold-based ternary logic synthesis method, carbon nanotube field effect transistors (CNTFETs) are intensively utilized to realize various ternary logic circuits due to the convenient control of threshold voltages. However, a general ternary logic gate requires three kinds of threshold voltage, whose specific values needs to be determined to optimize the delay and power performance. In this paper, an unbalanced ternary full adder based on ternary cycling gates is presented. Beneficial from the ternary arithmetical algorithm, the circuit complexity of the ternary adder has been largely simplified with only 93 transistors involved, which is much less than previous works. Besides, the optimal threshold voltage combination method has been investigated to optimize the circuit power-delay-product (PDP), and the lowest PDP of 12.55 aJ is achieved.

Original language	English
Title of host publication	2023 6th World Symposium on Communication Engineering, WSCE 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	98-102
Number of pages	5
ISBN (Electronic)	9798350339505
DOIs	https://doi.org/10.1109/WSCE59557.2023.10366016
Publication status	Published - 2023
Externally published	Yes
Event	6th World Symposium on Communication Engineering, WSCE 2023 - Thessaloniki, Greece Duration: Sept 27 2023 → Sept 29 2023

Publication series

Name	2023 6th World Symposium on Communication Engineering, WSCE 2023

Conference

Conference	6th World Symposium on Communication Engineering, WSCE 2023
Country/Territory	Greece
City	Thessaloniki
Period	9/27/23 → 9/29/23

Bibliographical note

Publisher Copyright:
© 2023 IEEE.

ASJC Scopus Subject Areas

Artificial Intelligence
Computer Networks and Communications
Computer Vision and Pattern Recognition
Hardware and Architecture
Safety, Risk, Reliability and Quality

Keywords

Multi-valued logic
ternary cycling gates
unbalanced ternary full adder

Access to Document

10.1109/WSCE59557.2023.10366016

Cite this

Zeng, Z., Zhao, G., Wang, X., Tay, B. K., & Huang, M. (2023). Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates. In 2023 6th World Symposium on Communication Engineering, WSCE 2023 (pp. 98-102). (2023 6th World Symposium on Communication Engineering, WSCE 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/WSCE59557.2023.10366016

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title = "Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates",

abstract = "Ternary logic system has attracted more and more attention because of its higher information density as compared with the binary system. In the prevalent multi-threshold-based ternary logic synthesis method, carbon nanotube field effect transistors (CNTFETs) are intensively utilized to realize various ternary logic circuits due to the convenient control of threshold voltages. However, a general ternary logic gate requires three kinds of threshold voltage, whose specific values needs to be determined to optimize the delay and power performance. In this paper, an unbalanced ternary full adder based on ternary cycling gates is presented. Beneficial from the ternary arithmetical algorithm, the circuit complexity of the ternary adder has been largely simplified with only 93 transistors involved, which is much less than previous works. Besides, the optimal threshold voltage combination method has been investigated to optimize the circuit power-delay-product (PDP), and the lowest PDP of 12.55 aJ is achieved.",

keywords = "Multi-valued logic, ternary cycling gates, unbalanced ternary full adder",

author = "Zhiwei Zeng and Guangchao Zhao and Xingli Wang and Tay, {Beng Kang} and Mingqiang Huang",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 6th World Symposium on Communication Engineering, WSCE 2023 ; Conference date: 27-09-2023 Through 29-09-2023",

year = "2023",

doi = "10.1109/WSCE59557.2023.10366016",

language = "English",

series = "2023 6th World Symposium on Communication Engineering, WSCE 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Zeng, Z, Zhao, G, Wang, X, Tay, BK & Huang, M 2023, Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates. in 2023 6th World Symposium on Communication Engineering, WSCE 2023. 2023 6th World Symposium on Communication Engineering, WSCE 2023, Institute of Electrical and Electronics Engineers Inc., pp. 98-102, 6th World Symposium on Communication Engineering, WSCE 2023, Thessaloniki, Greece, 9/27/23. https://doi.org/10.1109/WSCE59557.2023.10366016

Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates. / Zeng, Zhiwei; Zhao, Guangchao; Wang, Xingli et al.
2023 6th World Symposium on Communication Engineering, WSCE 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 98-102 (2023 6th World Symposium on Communication Engineering, WSCE 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates

AU - Zeng, Zhiwei

AU - Zhao, Guangchao

AU - Wang, Xingli

AU - Tay, Beng Kang

AU - Huang, Mingqiang

PY - 2023

Y1 - 2023

N2 - Ternary logic system has attracted more and more attention because of its higher information density as compared with the binary system. In the prevalent multi-threshold-based ternary logic synthesis method, carbon nanotube field effect transistors (CNTFETs) are intensively utilized to realize various ternary logic circuits due to the convenient control of threshold voltages. However, a general ternary logic gate requires three kinds of threshold voltage, whose specific values needs to be determined to optimize the delay and power performance. In this paper, an unbalanced ternary full adder based on ternary cycling gates is presented. Beneficial from the ternary arithmetical algorithm, the circuit complexity of the ternary adder has been largely simplified with only 93 transistors involved, which is much less than previous works. Besides, the optimal threshold voltage combination method has been investigated to optimize the circuit power-delay-product (PDP), and the lowest PDP of 12.55 aJ is achieved.

AB - Ternary logic system has attracted more and more attention because of its higher information density as compared with the binary system. In the prevalent multi-threshold-based ternary logic synthesis method, carbon nanotube field effect transistors (CNTFETs) are intensively utilized to realize various ternary logic circuits due to the convenient control of threshold voltages. However, a general ternary logic gate requires three kinds of threshold voltage, whose specific values needs to be determined to optimize the delay and power performance. In this paper, an unbalanced ternary full adder based on ternary cycling gates is presented. Beneficial from the ternary arithmetical algorithm, the circuit complexity of the ternary adder has been largely simplified with only 93 transistors involved, which is much less than previous works. Besides, the optimal threshold voltage combination method has been investigated to optimize the circuit power-delay-product (PDP), and the lowest PDP of 12.55 aJ is achieved.

KW - Multi-valued logic

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ER -

Low Power-Delay-Product Ternary Adder with Optimized Ternary Cycling Gates

Abstract

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Bibliographical note

ASJC Scopus Subject Areas

Keywords

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