Study of charge distribution and charge loss in dual-layer metal-nanocrystal-embedded high-κ/SiO ₂ gate stack

In this work, we present a comprehensive experimental study of charge loss mechanisms in a dual-layer metal nanocrystal (DL-MNC) embedded high-κ/SiO ₂ gate stack. Kelvin force microscopy characterization reveals that the internal-electric-field assisted tunneling could be a dominant charge loss mechanism in DL devices that mainly depends on the charge distribution in two MNC-layers and inter-layer dielectric (ILD) thickness between the two layers of nanocrystals. Our findings suggest that an optimized DL-MNCs embedded memory cell could be achieved by defining the ILD thickness larger than the average MNC-spacing for enhancement of retention ability in MNC embedded gate stacks. It implies the possibility of reducing MNC spacing in DL structure of scaled memory devices by controlling the thickness of ILD.