Study of spacer architecture and current leakage aspects of sub-micron self-aligned silicide process

Gate to source/drain leakage is a major concern especially for deep sub-micron salicide (self-aligned silicide) process. The tiny (≈0.1 μm) spacer between poly-Si gate and active region serves to offset the low-doped drain (LDD) ion-implantation and also provide isolation between poly-Si gate and active region. Therefore it plays an important role and determines the robustness of salicide process. Besides, formation of silicide on sub-micron poly-Si gate, junction leakage, reduction of junction consumption and process compatibility are some other key issues involved in optimizing the salicide process for deep sub-micron CMOS devices. In this paper, the results of the investigation on the performance of different spacer architectures will be presented, including conventional TEOS spacer, nitride spacer and a novel SiO₂/Si₃N₄ bilayer L-shape spacer.