Uniform delayering of copper metallization

Y. W. Siah, Y. J. Hong, Q. Liu, H. B. Kor, C. L. Gan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization removal while reducing edge rounding on the sample during sample preparation that will preserve the integrity of the layers for further failure analysis.

Original languageEnglish
Title of host publicationProceedings of the 2013 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2013
Pages166-169
Number of pages4
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2013 - Suzhou, China
Duration: Jul 15 2013Jul 19 2013

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference2013 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2013
Country/TerritoryChina
CitySuzhou
Period7/15/137/19/13

ASJC Scopus Subject Areas

  • Electrical and Electronic Engineering

Keywords

  • copper metallization
  • Delayering
  • polishing
  • sample preparation

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