@inproceedings{d53f12a74aac4e2984db3960c354300c,
title = "Uniform delayering of copper metallization",
abstract = "Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization removal while reducing edge rounding on the sample during sample preparation that will preserve the integrity of the layers for further failure analysis.",
keywords = "copper metallization, Delayering, polishing, sample preparation",
author = "Siah, {Y. W.} and Hong, {Y. J.} and Q. Liu and Kor, {H. B.} and Gan, {C. L.}",
year = "2013",
doi = "10.1109/IPFA.2013.6599147",
language = "English",
isbn = "9781479912414",
series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",
pages = "166--169",
booktitle = "Proceedings of the 2013 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2013",
note = "2013 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2013 ; Conference date: 15-07-2013 Through 19-07-2013",
}