Void formation in titanium desilicide/p⁺ silicon interface: Impact on junction leakage and silicide sheet resistance

We have observed the formation of voids at the interface of TiSi₂/p⁺-Si after the titanium-salicidation process in a deep-sub-micron CMOS technology. In our study, most of the voids occurred at the intersection of the polycrystalline TiSi₂ grain boundary with the p⁺ Si substrate and had an extended defect into the p⁺ Si substrate. In some cases, for voids that were not located at the TiSi₂ grain boundary, the substrate defects extended from the void/p⁺-Si interface into the silicide film, resulting in micro-twin defects. In addition, discrete and isolated defects were found at the bird's beak tips, which are most likely due to dislocation loops. However, its density was very low. Our investigation shows that void formation is relatively sensitive to the BF₂⁺ implant and p⁺ junction annealing temperature, and can be completely avoided by subjecting the p⁺ junctions to a high temperature anneal at 850 °C for 45 min prior to the salicidation process. We attribute these voids to the fluorine-related precipitates, in which the fluorine is from the BF₂⁺ ion implantation. It is believed that the formation of substrate defects is the root cause of high junction leakage observed in the pMOSFET devices, and the leakage can be substantially reduced by 1-2 orders of magnitude with the extra high temperature anneal. On top of that, the distribution of the sheet resistance of the Ti-salicided p⁺-Si becomes tighter.