Voltage-balance limits in four-level diode-clamped converters with passive front ends

Josep Pou*, Rafael Pindado, Dushan Boroyevich

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

5 Citations (Scopus)

Abstract

Multilevel diode-clamped converters with more than three levels cannot maintain voltage balance in the DC-link capacitors for some operating conditions due to the existence of DC currents in the middle points. Since capacitors arc either completely charged or discharged for those conditions, this circumstance severely limits practical application of these converters. The limit explored in this work is that the four-level converter cannot achieve voltage balance. Proper redundant vectors are selected in the space-vector diagram so that a quadratic parameter related to the currents in the middle points is minimized.

Original languageEnglish
Pages898-902
Number of pages5
DOIs
Publication statusPublished - 2002
Externally publishedYes
EventProceedings of the 2002 28th Annual Conference of the IEEE Industrial Electronics Society - Sevilla, Spain
Duration: Nov 5 2002Nov 8 2002

Conference

ConferenceProceedings of the 2002 28th Annual Conference of the IEEE Industrial Electronics Society
Country/TerritorySpain
CitySevilla
Period11/5/0211/8/02

ASJC Scopus Subject Areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Keywords

  • Four-level inverter
  • Multilevel inverter
  • Nearest vector
  • Parameter minimization
  • Passive front ends
  • Space-vector modulation
  • Voltage balance

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